1. Field
Embodiments of the present invention relate to the electronics manufacturing industry and more particularly to the process of etching a workpiece with a plasma etch tool.
2. Discussion of Related Art
As high volume manufacturing of microelectronics reaches the 65 nanometer (nm) technology node, the critical dimension (CD) requirement of all features in the front end of line (FEOL) and back end of line (BEOL) becomes increasingly demanding. 65 nm features are typically much smaller than the lithographically printed dimension. The standard technique for shrinking a lithographically defined dimension is pattern trimming, which is extensively used to extend the life of a given lithography technology. Pattern trimming removes a portion of the mask pattern, making the pattern smaller. This technique however is only useful for line patterns and not spaces between lines or via openings because the spaces between the lines and via openings only get larger when pattern trimming is performed. Thus, while the gate electrode patterning and etching processes are able to employ pattern trimming to achieve a sub-65 nm gate CD, contact or via patterning and etching processes have difficulty reaching sub-100 nm dimensions. Therefore, the trench and via CDs in the BEOL have become a critical path to further scaling of logic and/or memory circuits.
Forming a sloped via profile in the layer etched during the main etch operation is a conventional method for reducing a via CD to less than the lithographically defined mask CD. The layer etched during the main etch is referred to herein as a “substrate layer.” An example of a substrate layer is an inter-level dielectric (ILD) layer employed in the BEOL. Generally, a sloped via profile can be achieved by etching the substrate layer with an etchant comprising a polymerizing process gas that deposits on the via sidewalls at an increasing rate as the etch front proceeds deeper into the layer during the etch (i.e. the via aspect ratio increases). The polymer deposition provides a slope reducing the CD at the bottom of the via relative to the CD at the top of the via etched into the substrate layer. In high volume manufacturing however, the main etch profile tapering method is limited by the phenomena known as “etch-stop,” wherein the etch front fails to advance with additional etch time once a particular aspect ratio is reached in the substrate layer. Etch-stop generally occurs when polymer begins to accumulate at the via bottom as well as the via sidewall. The amount of etch profile tapering is limited by the aspect ratio of the via and therefore the magnitude of the via CD reduction possible from profile tapering declines as the lithographically defined via mask opening (i.e. top CD) shrinks. Thus, for a via mask with a lithographic CD of approximately 120 nm, process interactions in the main etch limit the via CD reduction achievable to somewhat less than 20 nm (i.e. less than 20%), as measured between the bottom of the via etched into the substrate layer and the lithographically defined mask CD.